1. Field of the Invention
The present invention relates to a digital receiver for use with a mobile station or the like of a digital mobile communication, in particular, to a frequency adjusting (automatic frequency control AFC) method and a frequency adjusting circuit that cause a reference frequency of a mobile station to follow a received frequency so as to stabilize the operation of the receiver.
2. Description of the Related Art
As disclosed in Japanese Patent Laid-Open Publication No. 6-6180, a conventional mobile station uses a super heterodyne type receiver. The receiver has a local oscillator that converts the received frequency into an intermediate frequency. The local oscillator comprises a reference oscillator such as a voltage control temperature compensated quartz oscillator (hereinafter referred to as TCXO) and a means (such as PLL synthesizer) that converts the oscillation frequency of the reference oscillator into an intermediate frequency. If the oscillation frequency of the local oscillator deviates from the reference frequency, the intermediate frequency also deviates from the predetermined frequency. Thus, the received signal cannot be accurately demodulated. To cause the reference frequency of the mobile station to follow the received frequency and stabilize the operation of the receiver, the oscillation frequency of the local oscillator should be prevented from deviating. To compensate the deviation of the oscillation frequency of the local oscillator, a frequency adjusting circuit (automatic frequency control circuit AFC) is used.
FIG. 1 is a block diagram showing an example of the structure of a double super heterodyne receiver having such an AFC circuit. In FIG. 1, reference numeral 1 is a receiving antenna. Reference numeral 2 is an amplifier. Reference numeral 3 is a first mixer. Reference numeral 4 is a second mixer. Reference numeral 5 is an intermediate frequency amplifier. Reference numeral 6 is a demodulator. Reference numerals 7 and 8 are voltage control oscillators. Reference numerals 9 and 10 are PLL synthesizers. These devices compose a pair of local oscillators. Reference numeral 11 is an A/D converter. Reference numeral 20 is an AFC circuit. Reference numeral 21 is a TCXO that supplies a reference frequency to the PLL synthesizers 9 and 10. The AFC circuit 20 comprises a calculating portion 23 and a D/A converter 22.
In this structure, a RF signal received from the receiving antenna 1 is supplied to the amplifier 2. The amplifier 2 amplifies the RF signal. The amplified signal is supplied to the first mixer 3. The first mixer 3 mixes the amplified signal with a first local oscillation signal F1 generated by the voltage control oscillator 7 and the PLL synthesizer 9 and outputs a first intermediate frequency signal IF1. Next, the first intermediate frequency signal IF1 is supplied to the second mixer 4. The second mixer 4 mixes the first intermediate frequency signal IF1 with a second local oscillation signal F2 generated by the voltage control oscillator 8 and the PLL synthesizer 10 and outputs a second intermediate frequency signal IF2. The second intermediate frequency signal IF2 is supplied to the intermediate frequency amplifier 5. The intermediate frequency amplifier 5 amplifies the second intermediate frequency signal IF2. The amplified signal is supplied to the demodulator 6. The demodulator 6 demodulates the amplified signal and outputs a demodulated signal. The intermediate frequency amplifier 5 monitors the level of the electric field intensity of the received signal and outputs a receiving electric field intensity (RSSI) as a DC voltage. The output signal of the intermediate frequency amplifier 5 is supplied to the A/D converter 11. The A/D converter 11 converts the DC voltage into a digital value and supplies the digital value as a receiving electric field intensity signal D2 to the calculating portion 23. In such a manner, the receiver monitors the receiving electric field intensity.
The AFC circuit 20 compensates the deviation of the oscillation frequency of the local oscillator so as to stabilize the intermediate frequencies of the intermediate frequency signals IF1 and IF2 corresponding to the frequency of the received signal. In other words, the calculating portion 23 that is composed of a counter and so forth calculates a compensation value of the deviation of the frequency with the intermediate frequency signal D1. FIG. 5 is a flow chart showing a calculating process performed by the calculating portion 23. In FIG. 5, the frequency deviation is measured with the intermediate frequency signal D1 by each received symbol unit. The measured frequency deviations are successively added for each received symbol unit that represents signal levels "0" and "1" of digital signals (at step S21). The number of received symbol units are monitored so as to obtain the average value of the frequency deviation of the intermediate frequency signal D1 in the receiving unit time as the received symbol units (at step S22). When the predetermined number of symbol units have been detected, the flow advances to step S23. When the predetermined number of symbols have not been detected, the flow returns to step S21. At step S23, the added value of the frequency deviations is divided by the number of samples in the receiving unit time and thereby the average value is obtained. The average value is referred to as a compensation value D3 of the local oscillator. The compensation value D3 that has been obtained in the just preceding receiving unit time is substituted with the compensation value D3 that has been newly obtained (at step S24).
The D/A converter 22 converts the updated compensation value D3 into an analog DC voltage. The analog DC voltage is supplied to the TCXO 21 so as to control the oscillation frequency f0 of the TCXO 21. An output signal of the TCXO 21 is supplied to the PLL synthesizers 9 and 10. The PLL synthesizers 9 and 10 control the oscillation frequencies of the voltage control oscillators 7 and 8 so as to feed back the oscillation frequencies of the local oscillators. Thus, the deviation of the oscillation frequency f0 of the TCXO 21 and the received frequency is decreased so that the oscillation frequency of the TCXO 21 follows the received frequency RF. In addition, since the oscillation frequencies of the local oscillators are based on one reference oscillator TCXO 21, the structure can be simplified.
In the conventional AFC circuit, regardless of the receiving condition of the received signal, the frequency deviation of the intermediate frequency is always measured. With the frequency deviation, the compensation value of the oscillation frequency is calculated. Thus, when the receiving electric field intensity is low due to fading and thereby the reliability of the frequency of the received frequency degrades, the oscillation frequency is compensated with the received frequency. Thus, the reliability of the compensation of the oscillation frequency degrades and thereby the oscillation frequency cannot be precisely compensated.
This problem becomes critical when the AFC is used for a general purpose European standard digital cellular phone (GSM). In European countries, the operating environments of the digital cellular phones largely vary country by country. In addition, fading takes place due to geographical conditions. Thus, the frequency deviation may be measured with an error of the intermediate frequency signal. Thus, even if the average value of the frequency deviations is obtained, it is affected by the error. The error affects the voltage control oscillator. Consequently, the oscillation frequency cannot be accurately compensated. Thus, the conventional AFC circuit and AFC method have problems as mentioned above description.